This application claims the priority benefit of Taiwan application serial no. 89120747, filed Oct. 5, 2000.
1. Field of the Invention
The present invention relates to a memory fabrication process. More particularly, the present invention relates to a self-aligned bit-line contact and node contact fabrication process.
2. Description of the Related Art
In the existing semiconductor fabrication processes, self-aligned contact (SAC) fabrication processes are often used to increase the alignment margin of the contact opening. The steps in the self-aligned contact process are as follows: a metal oxide semiconductor (MOS) gate and a cap layer above the gate are formed. A spacer is formed on a sidewall of the gate and cap layer. A dielectric layer is deposited over the substrate. A lithography and an etching process are conducted, to etch a self-aligned contact opening in the dielectric layer, on opposite sides of the gate. The self-aligned contact opening has a width greater than the distance between the gates, to assure that the source/drain region of the MOS is exposed. During the etching process, the gate are protected by the cap layer and the spacer. Thus, the gate is not exposed. The self-aligned contact is very wide. Consequently, even if there is a significant error in alignment, the contact opening formed in later steps is able to make contact with the source/drain region, which indicates that the alignment margin of the self-aligned contact is very high.
In the fabrication process of a memory, the self-aligned contact openings that must be formed above the source/drain region in the MOS of the memory cell are the self-aligned bit-line contact and self-aligned node contact, respectively. In the memory, gate contacts are located on some periphery MOS gates to form an electrically connection with the periphery gate contacts, so that to control the turn-on and turn-off of the periphery MOS can be controlled. The fabrication process of a self-aligned contact and periphery gate contact in a conventional memory is outlined below.
As shown in FIG. 1A, a substrate 100 having memory cell MOS 120 and periphery MOS active region 110 is provided, wherein gate dielectric layer 122 has been formed over periphery MOS active region 110, periphery MOS gate 130a has been formed over gate dielectric layer 122, cap layer 133a, composed of silicon nitride, has been formed over periphery MOS gate 130a and lightly doped drains (LDD) 150 have been formed in the substrate on opposite sides of MOS gate 130a. Memory cell MOS 120 includes gate dielectric layer 122, memory cell MOS gate 130b above gate dielectric layer 122, cap layer 133b, composed of silicon nitride, above memory cell MOS gate 130b, and memory cell source/drain region 154 in substrate 100 on opposite sides of memory cell MOS gate 130b. Isolation layer 120 isolates memory cell MOS 120. Conformal liner oxide layer 142 and a silicon nitride layer (not shown) are formed sequentially over substrate 100. Liner oxide layer functions to reduce the stress of the silicon nitride layer. An anisotropic etching operation is performed on the silicon nitride layer, to form spacer 143a on the sidewall of the periphery MOS gate 130a and cap layer 133a. At the same time spacer 143b is formed on the sidewall of memory cell MOS gate 130b and cap layer 133b. It should be pointed out that the specification uses the processing steps of periphery MOS active region 110 to represent the processing steps used for the NMOS active region and PMOS active region, in the periphery circuit. In this manner, the description can further simplified.
As shown in FIG. 1B, two photolithographic processes are performed respectively on the NMOS active region and PMOS active region, in order to form photoresist layer 158, which covers memory cell MOS 120. As mentioned above, the specification uses the processing steps of periphery MOS active region 110 to represent processing steps used for the NMOS active region and PMOS active region, in the periphery circuit. Thus, photoresist layer 158 represents the two layers formed as a result of two photolithographic processes on the top portion of the memory cell MOS 120. Using photoresist layer 158, cap layer 133a and spacer 143a as a mask, ions 159 are implanted to form a periphery source/drain region in substrate 100, on opposite sides of spacer 143a. This step completes the fabrication of periphery MOS 110a. 
The specification uses the processing steps of periphery MOS active region 110 to represent processing steps used for the NMOS active region and PMOS active region, in the periphery circuit. Thus, the etching of spacer 143a and the step of implanting ions 159, represent each spacer etching step and ion implantation step for both the periphery NMOS active region and PMOS active region.
As shown in FIG. 1C, substrate 100 is covered by silicon oxide layer 170. A third photolithography and an etching process are performed to form self-aligned bit-line contact opening 175, self-aligned node contact opening 176, and periphery gate contact opening 177 in silicon oxide layer 170. At the same time, liner oxide layer 142, exposed by self-aligned bit-line contact opening 175 and self-aligned node contact opening 176, is removed. Self-aligned bit-line contact opening 175 and self-aligned node contact opening 176 expose memory cell source/drain region 154. The width of contact openings 175 and 176 is greater than the distance between memory cell MOS gate 130b. Periphery gate contact opening 177 exposes cap layer 133a of periphery MOS 110a. 
As shown in FIG. 1D, a fourth photolithographic process is performed to cover the memory cell MOS 120 with photoresist layer 180 used to protect cap layer 133b and spacer 143b of the memory cell MOS. A silicon nitride etching step is performed to etch through cap layer 133a of the memory MOS cell, exposing periphery MOS gate 130a, in order to connect MOS gate 130a and the contact opening, formed in a subsequent step.
The above description and accompanying illustrations, reveal a characteristic in the fabrication process of a conventional memory self-aligned contact opening and periphery gate contact opening. Between the completion of memory cell source/drain region 154 and the lightly doped drain (LDD) 150 of periphery MOS 110a and the completion of contact openings 175, 176, and 177, a total of four photolithographic processes are performed. First, during the formation of periphery source drain region 160, two photolithographic processes are required. During the formation of periphery gate contact opening 177 and self-aligned bit-line (node) contact openings 175(176), a third photolithographic process is required. During the etch-through of cap layer 133a of the periphery MOS a fourth photolithographic process is required. The excessive number of photolithographic etching steps, makes the conventional fabrication process more complicated. Additionally, because a great portion of the cap layer composed of silicon nitride may be consumed during the etching of the self-aligned bit-line (node) contact opening 175 (176), cap layer 133b must be rather thick, which often causes excessive stress.
The present invention provides a self-aligned bit-line contact opening and node contact opening fabrication process, that only requires three photolithographic etching steps to form the periphery MOS source/drain region, the periphery gate contact opening and the self-aligned bit-line (node) contact opening, and etching of the cap layer above the periphery MOS gate. The steps of the fabrication process are as follows: a substrate is provided having a periphery MOS active region and memory cell MOS, wherein the periphery MOS active region has a first gate, and a cap layer above the first gate, and further wherein the memory cell MOS includes a second gate, a second cap layer above the second gate, and a second memory cell source/drain region in the substrate on opposite sides of the second gate.
A conformal insulation layer is then formed above the substrate. The material of the insulation layer is similar to the material of the first and second cap layers. The memory cell MOS is covered with a photoresist layer. Using the photoresist layer as a mask, anisotropic etching is performed on the insulation layer above the periphery MOS active region, to form a first spacer on a sidewall of the first gate and first cap layer. Using the photoresist, the first spacer, and the first cap layer as a mask, ions are implanted to form a periphery source/drain region in the substrate on opposite sides of the first spacer. This step completes the fabrication of a periphery MOS.
The photoresist layer is then removed. A dielectric layer is deposited over the substrate. A self-aligned bit-line contact opening and a self aligned node contact opening are formed in the dielectric layer on opposite sides of the second gate, to expose part of the insulation layer. At the same time, a periphery gate contact opening is formed in the dielectric layer above the first gate, to expose part of the first cap layer. Anisotropic etching is performed on the insulation layer of the self-aligned bit-line contact opening and the self-aligned node contact opening to form a second spacer on a sidewall of the second gate and second cap layer. At the same time the cap layer within the periphery gate contact opening is etched through, which exposes the first gate.
In the present invention, the material of the dielectric layer can be silicon oxide. The fabrication method further includes the step of forming a conformal liner oxide layer before forming the insulation layer above the substrate, and exposing the liner oxide layer after the second spacer has been formed. Additionally, the periphery MOS of the present invention further includes a lightly doped drain (LDD) in the substrate on opposite sides of the first gate. Moreover, the periphery contact opening can be a periphery bit-line contact opening for example.
In the fabrication process of a self-aligned bit-line contact opening and node contact opening of the present invention, the step of etching the memory cell MOS spacer is combined with the later step of etching through the periphery MOS cap layer. Thus, it is not necessary to use a fourth photolithographic process to protect the region of the memory cell MOS. That is to say, the number of photolithographic processes required can be reduced to three. As the self-aligned bit-line (node) contact opening are being etched, the first cap layer above the memory cell MOS gate can provide protection. Additionally, the insulation layer above the cap layer can serve as protection. Thus, the thickness of the first cap layer can be reduced, which results in reduced stress. The present invention has an additional feature. The etching of the periphery MOS spacer and ion implantation step of the periphery MOS source/drain region are performed using the same photoresist as a mask and, thus, does not increase the number of photolithographic processes.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.